Bilingual edition: English is preserved and Chinese follows each unit. Terminology uses the confirmed v20260916 glossary; automated semantic review remains traceable.
中英双语版：英文原文完整保留，中文紧随对应单元；术语采用 v20260916 确认表，自动语义审校结果可追溯。

Binary Counting

二进制计数

A binary counter can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, and so on down to the fourth cell. This produces a binary number equal to the number of cycles of the input clock signal. This device is sometimes called a "ripple through" counter. The same device is useful as a frequency divider.

一个二进制计数器可以由J-K触发器构成，通过将一个单元的输出连接到下一个单元的时钟输入。每个触发器的J和K输入设置为1，以在时钟输入的每个周期内产生翻转。对于第一个单元的每个两次翻转，第二个单元会产生一次翻转，依此类推，直到第四个单元。这会产生一个二进制数，其值等于输入时钟信号的周期数。这种设备有时也被称为“级联计数器”。同一设备也可用作频率分频器。
Index

Electronics concepts

Digital Circuits

Reference
Tocci
Digital Systems, Sec 5-19.
索引 电子概念 数字电路 参考 Tocci 数字系统，第5-19节。
 
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BCD or Decade Counter

BCD或十进制计数器

A BCD counter or decade counter can be constructed from a staight binary counter by terminating the "ripple-through" counting when the count reaches decimal 9 (binary 1001). Since the next toggle would set the two most significant bits, a NAND gate tied from those two outputs to the asynchronous clear line will start the count over after 9.

一个BCD计数器或十进制计数器可以通过将直通二进制计数器的“级联计数”在计数达到十进制9（二进制1001）时终止来构造。由于下一次翻转会设置两个最高有效位，将两个输出通过NAND门连接到异步清零线将使计数器在9之后重新开始计数。
 Index

Electronics concepts

Digital Circuits

Reference
Tocci
Digital Systems, Sec 7-2.
索引 电子概念 数字电路 参考 Tocci 数字系统，第7-2节。
 
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Frequency Division

频分

A frequency divider can be constructed from J-K flip-flops by taking the output of one cell to the clock input of the next. The J and K inputs of each flip-flop are set to 1 to produce a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in the second cell, so its output is at half the frequency of the first. The output of the fourth cell is 1/16 the clock frequency. The same device is useful as a binary counter.

一个频率分频器可以由J-K触发器构成，通过将一个单元的输出连接到下一个单元的时钟输入。每个触发器的J和K输入设置为1，以在每个时钟周期内产生翻转。对于第一个单元的每个两个翻转，第二个单元会产生一个翻转，因此其输出频率是第一个单元的一半。第四单元的输出频率是时钟频率的1/16。同一设备也可用作二进制计数器。
Index

Electronics concepts

Digital Circuits

Reference
Tocci
Digital Systems, Sec 5-19.
索引 电子概念 数字电路 参考 Tocci 数字系统，第5-19节。
 
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Counter and Decoder

计数器和解码器

The 14-pin 7490 counter chip and the 16-pin decoder chip are often used together to drive 7-segment displays.

14脚的7490计数器芯片和16脚的译码器芯片常一起使用以驱动七段显示器。
 Index

Electronics concepts

Digital Circuits

Reference
Mims, Getting started...
p. 90,117
索引 电子概念 数字电路 参考 Mims, Getting started... p. 90,117
 
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