Clocked Set-Reset Flip-flop

时钟置位复位边沿触发器

示例输出

When the signal line S goes high, the other line to the NAND gate from the pulse steering circuit must also be high for it to generate a low output. Likewise, a clock pulse must have the reset NAND gate high to receive a high RESET pulse. Therefore all transitions are synchronized to the clock.

当信号线S变高时，从脉冲选择电路到NAND门的另一条线路也必须变高，以便该门产生低电平输出。同样，时钟脉冲必须使复位NAND门处于高电平，以便接收高电平的复位脉冲。因此，所有转换都同步于时钟。

Set-reset Flip-flop

置位-复位翻转器

NAND-gate Latch

NAND逻辑门锁存器

Index

Electronics concepts

Digital circuits

索引电子学概念数字电路

HyperPhysics*****Electricity and magnetism

HyperPhysics ***** 电磁学

R Nave

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Pulse-Steering Circuit

脉冲定向电路

In the case of the J-K flip-flop, the pulse steering circuit is tied to the output lines past the NAND gate latch. This gives it the toggle action when J and K are both high.

在J-K触发器的情况下，脉冲选择电路连接到NAND门锁存器之后的输出线上。这使得当J和K都为高电平时，它具有翻转作用。

In order to add clock synchronization to a flip-flop, a ciruit is used to apply the clock pulses to the flip-flop. To convert a NAND gate latch to a clocked S/R flip-flop, two NAND gates may be used as above left to enable an input pulse on either the S or R lines to trigger a transition.

为了给触发器添加时钟同步功能，会使用一个电路将时钟脉冲施加到触发器上。要将一个NAND门锁存器转换为时钟控制的S/R触发器，可以如上左图所示使用两个NAND门，以使在S或R线上施加一个输入脉冲以触发状态变化。