The set/reset type flip-flop is triggered to a high state at Q by the "set" signal and holds that value until reset to low by a signal at the Reset input. This can be implemented as a NAND gate latch or a NOR gate latch and as a clocked version.

置位/复位型触发器在接收到“置位”信号时被触发至Q为高电平，并在复位信号作用下保持该状态。这可以实现为NAND门锁存器或NOR门锁存器，也可以实现为时钟版本。

One disadvantage of the S/R flip-flop is that the input S=R=0 gives ambiguous results and must be avoided. The J-K flip-flop gets around that problem.

S/R触发器的一个缺点是，当输入S=R=0时会产生歧义结果，必须避免。J-K触发器解决了这个问题。